PicProdigy®-CL-PMC

PicProdigy®-CL-PMC is a frame grabber supporting the Camera Link standard interface. This high-speed board can be used with both line-scan and area-scan Camera Link compatible cameras. It is suitable for both color and monochrome applications, and supports high-speed and high-resolution. It incorporates the CLP (Configurable Logic Processor) which supports user configurable hardware modules that implement functions such as pixel gain/offset, convolution, sobel, etc. PicProdigy®-CL-PMC is cost effective, compact and high performance, meeting the demanding requirements of diverse image processing and machine vision applications. It is a member of the LV Camera Link Family of products.

PicProdigy®-CL-PMC main highlights:

  • PMC form factor
  • Camera Link cameras
  • 1 base camera
  • +3.3V 32/64-bit, 33/66MHz PCI
  • extensive general purpose input/output
  • camera power
  • 32MB 0.7GB/s advanced features frame buffer
  • multiple hardware LUTs
  • user configurable hardware algorithm acceleration
  • LV-SDS and 3rd party software support

 

PicProdigy-CL-PMC

Architecture

A comprehensive array of on-board features include Camera Link interface for 1 base camera @ 85 MHz, large LUTs, multi-taps/packed pixel reformatting, color/monochrome format conversion, 32MB 0.7GB/s frame buffer with advanced features, 32/64-bit, 33/66 MHz PCI bus interface with 16 DMA channels and user configurable hardware modules (via CLP). The frame buffer ensures no data loss under varying operating system conditions by virtue of its memory size and its ability to generate interrupts to the user application that flag dynamic image buffer watermark depth thresholds.

PicProdigy-CL-PMC, board architecture

PicProdigy®-CL-PMC architecture is user friendly, em-ploying innovative re-programmable flash memory and FPGA (Field Programmable Gate Array) technologies. This allows the user to reconfigure the on-board hardware via downloadable software updates. The flash memory can also be used for security coding to prevent unauthorized copying of user application proprietary technology.

Image Acquisition & Conditioning

Camera Link Interfaces

Simultaneously supports 1 base (3 ¡Ñ 8-bit or 2 ¡Ñ 8/10/12-bit or 1 ¡Ñ 8/10/12/14/16-bit monochrome or 24-bit RGB) camera. Area-scan up to 64K ¡Ñ 64K and line-scan up to 64K ¡Ñ infinity with input frequencies up to 85 MHz.

Camera Link control lines for asynchronous reset and exposure control.

Camera Link serial ports for camera setup and control.

General Purpose input/output Interfaces

Camera power, LVDS/TTL and opto-coupler input/outputs are accessible via the PCI backplate 6-pin hirose connector or via a 40-pin header socket on the PCB top edge.

Camera power is provided for 1 camera and is +5V or +12V selectable. These are available on both Hirose and header connectors. Resettable fuses of 1A are provided for both.

LVDS and TTL inputs/outputs share physical pins. Selection of direction and standard is via software control. Up to 3 LVDS or TTL pairs are available. Each pair can be selected as 1 LVDS input or 1 LVDS output or 2 TTL inputs or 2 TTL outputs. One pair is on the hirose connector 2 pairs on the header connector. There is also 1 unique TTL input/output on the hirose connector.

8 opto-coupler inputs and 8 outputs are provided on the header connectors. These have built-in resistors to minimize external components.

All I/O pins are protected by over/under voltage protection devices clamping to +5V and ground.

Application note «External trigger and flash» gives good overview of applications involving external devices such as trigger and flash and about connecting such devices to the frame grabber.

LUTs

Multiple hardware LUTs are provided for user configuration as dual 4K ¡Ñ 12 or dual 256 ¡Ñ 8 (FPGA internal) or dual 256K ¡Ñ 18 (FPGA external). Multiple banks are supported for dynamic data changes.

Configurable Logic Processor (CLP)

PicProdigy®-CL-PMC provides user configurable hardware via the CLP. Functions such as Bayer color decoder, pixel gain/offset correction, convolution, sobel, etc are available. Using this on-board facility is an economical and fast solution to high bandwidth per pixel operations that overwhelm the host CPU's bandwidth.

Data Storage and Transfer

Frame Buffer

A 32MB frame buffer is provided to buffer and re-format the pixel data grabbed from the camera, before passing it to the PCI bus DMA. A sophisticated controller facilitates combining of camera taps into a raster output to the PCI DMA. Features include:

  • auto line and frame length detection
  • multi-tap pixel rasterization
  • buffer fill level water mark interrupt
  • excellent bandwidth of 0.7 GB/s

DMA Controller

Output data from the Frame Buffer is passed to the DMA controller. This innovative design allows up to 16 DMA channels to be user defined, controlling data burst transfers over the PCI bus. Each DMA channel can also define a Region-Of-Interest within the data stream and can also re-transmit the data to multiple destinations on the PCI bus.

In conjunction with the color/monochrome data formatter, various formats of the image data can be transferred to host memory or graphic display memory.

Host Bus Interface

A +3.3V compatible PCI bus interface is provided that can operate at 32/64-bit, 33/66MHz. This provides hi-end PCI bus bandwidth at an affordable price.

Flash Memory Controller

The on-board flash memory stores the various configurations of the board that are loaded at power-up and also any software technology security information (software dongle).

Applications

  • industrial image processing
  • web inspection
  • traffic vision systems
  • medical imageing
  • and many more...

Digital I/O Interface

General Purpose I/O

PicProdigy®-CL-Mono-PMC board provides various general purpose input/output interfaces. Location and pinout of the connectors is described section Connector Description.

Camera power, LVDS/TTL and opto-coupler input/outputs are accessible via the PCI backplate 6-pin Hirose connector or via a 40-pin header socket on the PCB top edge.

Camera power is provided for 1 camera and is +5V or +12V selectable (via on-board jumpers). These are available on both Hirose and header connectors. Resettable fuses are provided for both.

LVDS and TTL inputs/outputs share physical pins (GPIO_P0..2, GPIO_N0..2). Selection of direction and standard is via software control. Up to 3 LVDS or TTL pairs are available. Each pair can be selected as 1 LVDS input or 1 LVDS output or 2 TTL inputs or 2 TTL outputs. One pair is on the Hirose connector and two pairs on the header connector. There is also 1 unique TTL input/output on the Hirose connector.

8 optocoupler inputs and 8 outputs are provided on the header connectors. These have built-in resistors to minimize external components.

The 8 opto inputs are grouped into 4 pairs (01/23/45/67), each pair having a common Anode (+) and 2 Cathode (-) pins. The 8 opto outputs are grouped into 2 banks (0..3/4..7), each with 4 outputs. The Collector pins (OptoCx) of one bank do have pull-up resistors to a common rail TAP24V_03/47 which must be connected to the desired operation voltage (+5..24V). The Emitter pins (OptoEx) are normally connected to the ground terminal of the external voltage source. More details about the optocoupler interface are provided in the section below.

All I/O pins are protected by over/under voltage protection devices clamping to +5V and ground.

Optocoupler Interface

For use in industrial environment, PicProdigy®-CL-PMC boards provide I/O signals isolated by use of optocouplers with variable 5V to 24V interface. To take full profit of this signal isolation, you have to connect the optocoupler to an external power supply.

The optocoupler input is prepared for input signals from 5 V to 24 V with the appropriate onboard serial resistors. The optooupler output is prepared for external voltage from 5 V to 24 V.

See also the following examples of optocoupler output. In industrial environment, signal levels of 24 V are usually needed.

Application note «External trigger and flash» gives good overview of applications involving external devices such as trigger and flash.

Software

Driver Software

Leutron Vision Software Development Suite, LV-SDS, is a software development package (Windows, Linux, VxWorks) that allows full control of all PicPort® and PicProdigy® products. The suite consists of Daisy - the basic software interface for PicPort®/PicProdigy® cards, Camera Editor - easy interactive setup of standard and non-standard cameras, DRAL - a library for handling specific time-critical tasks, Orchid - high level library (DLL or OCX) for quick and easy design of PicPort®/PicProdigy® applications, TWAIN Driver and Video for Windows - provide a simple interface between Leutron Vision hardware and other office and image manipulation programs (e.g. MS Office, CorelDRAW, etc.).

The software products come complete with a set of demo programs and additional examples with source code as a guide to the programmer in developing particular applications. To obtain more comprehensive information please download the LV-SDS manual.

Third Party Software

Several well-known third party packages for real-time image processing and analysis are also supported. The packages include HALCON, Activ Vision Tools, NeuroCheck, and others. Please refer to our detailed software brochure (PDF) for more details.

Connector Description, Wiring Schemes

Connector positions

This chapter provides description of the connectors, jumpers and DIP switches of PicProdigy®-CL-PMC. The following image show locations and pin #1 positions of all the connectors described below.

Camera connector

Standard CameraLink connectors for base configuration. Please refer to official CameraLink specification to get the connector pinout.

Basic I/O connector

Hirose 6-pin female connector with camera power output and general purpose I/O signals; the connector is accessible from the backplate of the board.

Pin Signal
1 +5V
2 +12V
3 TTL_IO
4 GPIO_P2
5 GPIO_N2
6 GND

Universal I/O Connector

Male 40-pin header socket (P8 on figure above) with camera power output, opto-coupler interface, and general purpose I/O; the connector is not directly accessible from the backplate of the board.

Note: The header socket connector may be connected via flat cable to a 37-pin D-sub connector (appearing for example on LVmPC back panel). The following table shows also the relevant pins on that connector.

Pin 1) Pin 2) Signal
1 1 Optocoupler 0, Input A, +5V Anode
2 20 Optocoupler 0, Input K Cathode (signal ground)
3 2 Optocoupler 1, Input A, +5V Anode
4 21 Optocoupler 1, Input K Cathode (signal ground)
5 3 Optocoupler 2, Input A, +5V Anode
6 22 Optocoupler 2, Input K Cathode (signal ground)
7 4 Optocoupler 3, Input A, +5V Anode
8 23 Optocoupler 3, Input K Cathode (signal ground)
9 5 Optocoupler 4, Input A, +5V Anode
10 24 Optocoupler 4, Input K Cathode (signal ground)
11 6 Optocoupler 5, Input A, +5V Anode
12 25 Optocoupler 5, Input K Cathode (signal ground)
13 7 Optocoupler 6, Input A, +5V Anode
14 26 Optocoupler 6, Input K Cathode (signal ground)
15 8 Optocoupler 7, Input A, +5V Anode
16 27 Optocoupler 7, Input K Cathode (signal ground)
17 9 Optocoupler 0, Output Collector
18 28 Optocoupler 0, Otuput Emitter
19 10 Optocoupler 1, Output Collector
20 29 Optocoupler 1, Otuput Emitter
21 11 Optocoupler 2, Output Collector
22 30 Optocoupler 2, Otuput Emitter
23 12 Optocoupler 3, Output Collector
24 31 Optocoupler 3, Otuput Emitter
25 13 Optocoupler 4, Output Collector
26 32 Optocoupler 4, Otuput Emitter
27 14 Optocoupler 5, Output Collector
28 33 Optocoupler 5, Otuput Emitter
29 15 Optocoupler 6, Output Collector
30 34 Optocoupler 6, Otuput Emitter
31 16 Optocoupler 7, Output Collector
32 35 Optocoupler 7, Otuput Emitter
33 17 TAP 5¡V24V External Power Supply for Optocoupler Outputs 0..3
34 36 TAP 5¡V24V External Power Supply for Optocoupler Outputs 4..7
35 18 +5V/+12V selectable (fused)
36 37 Ground
37 19 GPIO_P0
38 nc GPIO_N0
39 nc GPIO_P1
40 nc GPIO_N1
1) Pin numbers for the 40-pin on-board connector
2) Pin numbers for the 37-pin D-sub connector on the optional conversion cable

Power Selector Jumper

A 3-pin male headers (S1) allowing to select the power output voltage that should be delivered to camera through the I/O connectors (see Basic I/O and Universal I/O connector descriptions above).

The table below shows how to select between the +5V and +12V voltages for camera power output.

Jumper connection Meaning
+5V voltage selected for camera power output
+12V voltage selected for camera power output

Control DIP Switches

The board possesses a DIP-switch device holding two switches (U7 on the figure above). Function description of the switches is described below. The pin marked as rectangle instead of an ellipse corresponds with OFF position of DIP-switch #1.

DIP-Switch Status Function
0 ON PCI gold bank boot select
OFF PCI gold bank boot disabled (default)
1 ON reserved
OFF reserved

PCI Gold Bank Protection (DIP Switch 0)

PCI Gold Banks should normally never be changed by the user. The prime function of the PCI Gold Banks is to guarantee a recovery mechanism after a Flash Bank programming cycle for an onboard FPGA has failed due to a system crash or power failure. In these cases the Flash Bank programming cycle can not be repeated without rebooting the system. However, since one or more Flash Banks may now contain corrupted FPGA configuration data it must ensured that these banks are not used for FPGA configuration after the next system reboot.

For this purpose DIP switch 0 of the Flash Controller (GoldBootSel) must be set to the 'ON' position. In GoldBoot mode the Flash Controller configures the PCI-FPGA from the Gold PCI Bank but leaves the Video-FPGA and CLP-FPGA idle. The Flash programming cycle can now be repeated. After the Flash programming has been completed successfully the GoldBootSel can be reset and the system must be power-cycled (not soft-reset) before the Flash Bank update takes effect.

Technical Specifications

Camera Link modes Base
Camera Link acquisition rate Up to 85 MHz per input
Camera scan modes Area-scan or line-scan
PCI bus form factor PMC
PCI bus interface +3.3V 32/64-bit, 33/66 MHz
PCI bus burst transfer rate 533 MB/s peak, 360 MB/s sustained
PCI bus DMA channels 16 with independent ROI and retransmit modes
On-board memory 32 MB DDR SDRAM, 1 MB SSRAM, 16 Mb flash
Color/monochrome data conversion RGB or monochrome target formats with various depths and data packing options
LUTs Dual 4K¡Ñ12 or quad 256K¡Ñ8 (FPGA internal) or dual 256K¡Ñ18 (FPGA external)
Frame buffer bandwidth 0.7 GB/s
Frame buffer features Low-latency input/output,
Multi-tap combining,
Up to 64K¡Ñ64K area-scan,
Up to 64K¡Ñinfinity line-scan,
Image fill level interrupt
CLP hardware functions Bayer decoding, gain/offset correction, convolution, sobel, etc.
TTL inputs * 7
TTL outputs * 7
LVDS inputs * 3
LVDS outputs * 3
Opto-coupled inputs 8
Opto-coupled outputs 8
Camera power Selectable +5V or +12V @ 1.0A
Camera power protection Resettable fuse
Board power requirements (excluding camera power) +5V @ 1.5A
Operating temperature range 0 ¢XC to 70 ¢XC
Relative humidity Up to 95 % (non-condensing)
FCC Class A
CE Class A
Dimensions PMC form factor 7.5 ¡Ñ 15 cm
*LVDS and TTL inputs and outputs share common pins and hence only one format can be selected for each pair of pins.

Complementary and Related Products

Supporting software

Comprehensive set of software tools consisting of video capture libraries and image processing libraries for Windows XP/2000/NT4, Windows Me/98/95 and for Linux. Please check especially the following ones:

Daisy
Video capture library of LV-SDS (Software Development Suite). Object oriented library of functions controlling all features of PicPort® and PicProdigy® boards.
Camera editor
An easy-to-use application enabling user to connect one of many predefined video sources or specify another, even nonstandard one.
DRAL
Extension libraries for Daisy providing real-time functionality of PicPort®/PicProdigy® frame grabbers.
Orchid
High level library for developing interactive applications with a few lines of code in visual tools like Microsoft Visual Basic, Borland Delphi, Borland C++ Builder, etc. Available as a DLL or as an OCX component.

Suitable Cameras

Please check the list of suitable cameras (CameraLink models) for use with PicProdigy®-CL-PMC. The link invokes page showing wide list of different suitable cameras, allowing you to specify more criterions and restrict the list only to the cameras exactly matching your needs.

Correspondent cables

All the necessary cables for connecting a camera to the framegrabber are available.

Related Frame Grabbers

PicPort®-Pro-CL-PMC
CameraLink frame grabber similar to PicProdigy-CL-PMC, but without the hardware algorithm accelerator.
PicPort®-Digital-PMC
Frame grabber with LVDS (RS422/RS644) digital interface.

LVmPC®

LVmPC® is an ultra compact, mobile image processing system for industrial and machine vision, based on standard PC technology and Leutron's frame grabber series. LVmPC® is available in a huge variety of different configurations.

Ordering Information

Ordering number Product Description
21030 PicProdigy®-CL-Mono-PMC CameraLink board for one base camera, on-board hardware algorithm accelerator, PMC standard
Expansion boards for LVmPC system
10600 PicProdigy®-CL-Mono for LVmPC PicProdigy®-CL-Mono-PMC, version for LVmPC
Complementary products
16028 LV-SDS Driver software developer's suit for Windows and Linux
15012 PCI-PMC adapter To operate a PMC module in a computer with standard PCI bus
15000 Potoelectric reflex switch set Ready to use with PicPort®-Mono/Stereo-PMC, consists of photoelectric reflex switch, self adhesive reflective tape and mounting parts
15012 Optocoupler test board Enables testing of the opto-isolated I/O functionality of all PicPort® framegrabbers
19152 Cab/3m/CL 3m Camera Link cable