MTP-2 Intelligent Subsystem
Description
- MTP-1/-2 (message transfer protocol) software subsystem for dual E1/T1 intelligent PMC/860 board
Standards Compliance
- ITU-T, Q.701, Q.703, Q.781
- ANSI T1.111.3
- Operating system support for Solaris 2.6 and VxWorks Tornado 1.0.1
- Support for four (4) simultaneous MTP-2 channels-fractional or non-fractional E1/T1
- Easy integration of any MTP-3 API to Force's StackWare MTP-2 link layer
- Trillium MTP-2 API compliance supported
- PMC (IEEE P1386) based hardware subsystem for easy integration with
- CompactPCI boards
- VME boards
- Proprietary board design
Highlights
The StackWare?MTP-2 protocol is a self-contained, pre-configured MTP-1 and MTP-2 software solution for use with the Force PMC/860 telecom controller. It includes Solaris and VxWorks?drivers.
The StackWare/MTP-2 software package frees you from hardware or I/O device specific programming and gives you a generic set of APIs for use in a single operating system. The protocol supports easy integration of MTP-3 or Signaling System No. 7 (SS7) upper-level stacks.
Force has tested this MTP-2 protocol for compliance with ITU-T, Q.701, Q.703, and Q.781 via I-NET tester.
StackWare MTP-2 protocol is targeted at SS7 gateway, VoIP gateway, wireless and AIN/IN infrastructure applications.
API Control
The MTP-2 binary product is API controlled. As illustrated above, the StackWare MTP-2 software package includes two principal parts: binary software running on a PMC/860 module and the Shared Memory interface running on the PCI Host. The Force API on the PCI Host provides the software interface to the application.
Message Transfer Part - Level 2 (MTP-2)
The StackWare Frame Relay control protocol provides status signaling for PVCs. It supports the User-Network Interface (UNI) and Network-Network Interface (NNI). The software supports ITU-T, ANSI and Frame Relay Forum.
LMI provides capabilities to manage and maintain PVCs, verify link integrity, and detect and correct errors. LMI supports maintenance of link integrity and management of end-to-end PVC establishment, deletion and propagation of link and PVC failures.
Configuration management
The StackWare MTP-2 product provides PMC/860 hardware configuration management functions such as control of PowerQUICC Multiplexer, Line Interface Unit, Clock Control and Layer 1 configuration. Supported service functions include Power-On-Self-Test, diagnostic and statistical operations.
The MTP-2 software supports up to four physical channels of MTP-2 to run in parallel-other channels can be routed to the TDM bus interface or can be routed to the PMC/860 memory (transparent mode).
Performance
StackWare MTP-2 has been benchmarked with one PMC/860 running at 66 MHz on MFIO-110 and Solaris 2.6 SPARC CPCI-522 at 300 MHz.
Configured systems support
StackWare MTP-2 with the PMC/860 supports a wide range of system configurations, including:
- VxWorks real-time environment for SS7 applications on VME- and CPCI-based Power PC boards. Integrate
MTP-3 and upper SS7, as well as H.110 and CPCI rear I/O for E1/T1
- A Solaris system, such as a Force CPCI-522, with MTP-3 and upper level SS7 equipped with StackWare
MTP-2 and a PMC/860
- Solaris SS7 applications with redundant link sets
Specifications
Product package
- CD-ROM
- Binary software for PMC/860, 66 MHz
- Host driver and APIs: Solaris 2.6 driver, VxWorks Tornado 1.0.1 driver
- Programmers guide (PDF file)
- License agreement for use with one PMC/860
- Installation guide
MTP-2 support
- Performance optimized Normal alignment procedure (ITU and ANSI)
- Normal alignment procedure (ITU and ANSI)
- Emergency alignment procedure
- Realignment on link failure
- Signal unit and alignment error rate monitors
- Multiple variants, including ITU 1988 and 1992 and ANSI 1988 and 1992
- Basic error correction method
- Preventive cyclic correction method (ITU and ANSI)
- Congestion control and congestion abatement
- Processor outage procedures (ITU and ANSI)
- Data flow regulation when system's resource utilization reaches configurable thresholds
Configuration management
- Power-On-Self-Test
- Triggered by power-on-reset
- Memory test (DRAM, SRAM, DPRAM)
- Basic I/O device test (Line I/F, Multiplexer, PCI bridge)
- Results available to the application
- E1/T1 Framer control
- AMI or HDB3 line code (for E1 lines)
- AMI or B8ZS line code (for T1 lines)
- Clock Control
- Select Clock source for local reference clock
- Set SCbus clock functions
- Define secondary clock sources
- Time Slot Multiplexer control
- Link Management Alarm Processing
- PowerQUICC control, including
- MTP-1 mode
- QMC mode (QUICC Multichannel Controller for HDLC)
- HDLC mode
- Transparent mode (user data to memory)
- PCI shared memory interface (device drivers)
- Diagnostics
- API based, accessible at run-time from host and via the debug port
- E1/T1 internal/external loopback
- Data path test for PowerQUICC, HDLC Controller, Multiplexer, Framer and internal/remote loopbacks
(supported also at runtime using unused timeslots)
- BERT (Bit Error Rate Test) Statistics
- Various statistical functions for physical layer and Layer 2
- Qualified carrier cards for PMC/860 with Stackware MTP-2
- VxWorks with PowerCore-6604
- VxWorks with PowerCore CPCI-6750
- Solaris 2.6 with SPARC CPCI-522 or CPU-50
- MFIO-110 support with Solaris
- Other configurations and operating systems on request
Standards compliance
- ITU-T Q.701, Q.703, Q.781
- ANSI T1.111.3
