LAPD Intelligent Subsystem

Description


Standards Compliance


- ITU-T, Q.920, Q.921

- Bellcore, SR-NWT-001959
- ETSI, ETS 300 102-1, ETS 300 102-2, ETS 300007, ETS 300 104
- Operating system support for Solaris 2.6 and VxWorks Tornado 1.0.1
- Support for QMC mode to run 64 LAPD physical channels in parallel
- PMC (IEEE P1386) based hardware subsystem for easy integration with CompactPCI boards
- VME boards
- Proprietary board designs


The StackWare LAPD protocol is a self-contained, pre-configured software solution for use with the Force

PMC/860 telecom controller. It includes Solaris?and VxWorks drivers.

The StackWare LAPD software package frees you from hardware or I/O device specific programming

and it gives you a generic set of APIs and a single operating system environment.

The protocol supports easy integration of LAPD.


Force has tested this LAPD protocol for compliance with TBR4 Layer 2 via HP PT 502 tester.

PMC (IEEE P1386) based hardware subsystem offers easy integration with CompactPCI VME and

proprietary board designs.

LAPD is targeted at wireless and data communication applications, including ISDN.

 

API Control

The LAPD binary product is API controlled. As illustrated, the StackWare LAPD package includes

two main parts: binary software running on a PMC/860 module and the Shared Memory interface running

on the PCI host. The Force API on the PCI host provides the software interface to the application.

 

LAPD control protocol

The StackWare LAPD control protocol supports the Link Access Procedure D (LAPD) on the user

(TE or DTE) or network side (NT or DCE). It also supports static TEI assignment.

StackWare LAPD also controls Layer 1 configuration, including data transfer in HDLC or transparent mode.

The following HDLC parameters are configurable: flag/idle generation, minimum number of flags

between frames,maximum frame, and CRC length and mask.

 

Configuration management

The StackWare LAPD product provides PMC/860 hardware configuration management

functions such as control of PowerQUICC? Multiplexer, Line Interface Unit, and Clock Control.

Supported service functions include Power-On-Self-Test, diagnostic and statistical operations.

When operating a PowerQUICC serial communication controller in single channel or QUICC

multichannel mode, the LAPD software supports a maximum of 64 parallel channels on a 66 MHz

PowerQUICC processor. It also supports channel-to-timeslot mapping in dynamic/static and single/dual modes.

Performance

StackWare LAPD has been benchmarked with one PMC/860 running at 66 MHz on MFIO-110 and

Solaris 2.6 SPARC CPCI-522 at 300 MHz to perform over 600 messages per second.


Configured systems support


StackWare LAPD with the PMC/860 supports a wide range of system configurations, including:

VxWorks real-time environment on VME- and CPCI-based Power PC boards

A Solaris system, such as a Force CPCI-522, equipped with StackWare LAPD and a PMC/860

 

Specifications

Product package

- CD-ROM

- Binary software for PMC/860, 66 MHz

- Host driver and APIs: Solaris 2.6 driver, VxWorks Tornado 1.0.1 driver

- Programmers guide (PDF file)

- License agreement for use with one PMC/860

- Installation guide

LAPD support

- User side support (TE or DTE)
- Network side support (NT or DCE)
- Static TEI assignment
- XID frame
- Standard three SAPI values (Q.930, X.25, Management) with extensions for up to 64 SAPIs
- Acknowledged and unacknowledged modes
- Broadcast data link connections
- Modulo 8 or modulo 128 sequencing
- Configurable HDLC parameters for flag/idle generation, minimum number of flags between frames 

  maximum frame and CRC length and mask

 

Configuration management

- Power-On-Self-Test
- Triggered by power-on-reset
- Memory test (DRAM, SRAM, DPRAM)
- Basic I/O device test (Line I/F, Multiplexer, PCI bridge)
- Results available to the application
- E1/T1 Framer control
- AMI or HDB3 line code (for E1 lines)
- AMI or B8ZS line code (for T1 lines)
- Clock Control
- Select Clock source for local reference clock
- Set SCbus clock functions
- Define secondary clock sources
- Time Slot Multiplexer control
- Link Management Alarm Processing
- PowerQUICC control, including
- QMC mode (QUICC Multichannel Controller for HDLC)
- HDLC mode
- Transparent mode (user data to memory)
- PCI shared memory interface (device drivers)
- Diagnostics
- API based, accessible at run-time from host and via the debug port
- E1/T1 internal/external loopback
- Data path test for PowerQUICC, HDLC Controller, Multiplexer, Framer and internal/remote loopbacks 

  (supported also atruntime using unused timeslots)
- BERT (Bit Error Rate Test) Statistics
- Various statistical functions for physical layer and Layer 2
- Qualified carrier cards for PMC/860 with StackWare LAPD
- VxWorks with PowerCore-6604
- VxWorks with PowerCore CPCI-6750
- Solaris 2.6 with SPARC CPCI-522 or CPU-50
- MFIO-110 support with Solaris
- Other configurations and operating systems on request

Standards compliance

- ITU-T Q.920, Q.921
- Bellcore SR-NWT-001959
- ETSI ETS 300 102-1, ETS 300 102-2, ETS 300007, ETS 300 104